SiGe provides higher carrier mobility than silicon (Si). SiGe fins of a FinFET reduce threshold voltage (Vt), thereby increasing the drive current that flows through the channel. However, an effective channel length (Leff) performance improvement with SiGe fins is difficult to achieve because of (i) relaxation of the SiGe fins from tunnel junction (TJ) etching; (ii) interface problems with gate oxide resulting in degrading of the roughness of the fins; (iii) p-type field effect transistor (PFET) gate-induced drain leakage (GIDL); (iv) density of interface trap (DIT); and (v) n-type field effect transistor (NFET) issues associated with the integration process to make SiGe fins, e.g., the nitride liner causing NFET leakage. In addition, yield is difficult to demonstrate with SiGe fins because of high static random access memory (SRAM) leakage and SiGe fin integration limitations, e.g., low temperature STI processing and crystalline defects.
A need therefore exists for methodology enabling forming a SiGe PFET channel without known complicated processing or difficulties.